Certain systems use shared resources such as shared memory and have processing nodes that operate according to a producer-consumer model where data is produced by one processing node and consumed by another processing node using shared resources. Further, write transactions to such shared resources can be ordered such that certain transactions are required to occur before other transactions.
The AXI (Advanced eXtensible Interface) protocol developed by ARM is an interconnected bus specification that in part uses ordered write transactions to shared resources to implement a producer-consumer model. When devices are connected to communicate through an AXI interconnection, these devices are required to satisfy specific AXI ordering rules in order to meet AXI protocol requirements when a write transaction occurs through the AXI interconnection from an AXI requester node to an AXI target node. For example, AXI ordering rules in part require that transactions carrying the same AXI identifier (AXI-ID) from an AXI requester to the same destination AXI target must occur in order, that transactions with the same AXI-ID from an AXI requester to a different destination AXI target must occur in order, that transactions with different AXI-IDs from an AXI requester to destination AXI targets can occur in any order, and that AXI non-buffered write transactions must wait for all previous AXI buffered write transactions with the same AXI-ID to complete.
Typically, each AXI requester takes on the responsibility for adhering to the AXI ordering requirements. For example, for producer-consumer behavior to work correctly under AXI ordering rules, the buffered writes with a given AXI-ID are required to complete in a particular write order. In this behavior, buffered writes for data are followed by a buffered write of a completion flag or a MSI buffered write with the same AXI-ID. These AXI buffered writes may also go to distinct targets within the interconnection requiring AXI write ordering. Typically, the AXI write ordering has been performed at an AXI entry logic block within the requester by stalling writes into the AXI interconnection to a new destination target until all previously issued writes to an old destination target have completed. This prior method, however, has produced large latencies, reduced bandwidth, and large buffering structures at the AXI entry logic block for AXI requesters.
Further, the stream of buffered writes from an AXI requester node, such as an input-output (IO) requester, may be interleaved such that they access multiple target devices, such as memory devices and/or other target devices. In this case, significant processing overhead and latency is required of the requester node to make sure that the stream of buffered AXI writes complete in the proper order as the requester node is responsible for adhering to the AXI ordering requirements.